The plot is drawn arbitrarily to 1 GHz.įigure 1. Figure 1 (c) uses a logarithmic x-axis to plot a similar transfer function for a PLL having a closed-loop bandwidth of 5 MHz. Below the Nyquist frequency, jitter frequencies falling inside the PLL loop bandwidth pass unattenuated, whereas jitter frequencies falling outside this bandwidth get attenuated by the response of the loop. Figure 1 (b) illustrates the PLL jitter-transfer function, whose low-pass filtering characteristic is mirrored across spectral boundaries at integer multiples of the Nyquist frequency, F S/2. Spectral components of jitter located above the Nyquist frequency (F S/2) alias, or fold back, below the Nyquist frequency after sampling. Therefore, the average sampling (F S) and input-clock frequencies (F IN) are equal. In this example, the phase detector samples its inputs at their rising-edge midpoints. Figure 1 (a) shows an example PLL whose phase detector compares corresponding input and feedback edges, and outputs a pulse proportional to their phase difference, which is then filtered to control a voltage-controlled oscillator. How PLLs Observe Phase NoiseĪ phase-locked loop (PLL) is a basic building block in many digital and RF systems. While discussed below in the context of PCI Express, this methodology is generally applicable to analyzing signals passing through any PLL-based system, including reference clocks in any high-speed serial-data communications standard. This article presents this methodology, which has been adopted into PCI Express 5.0. In addition, Version 0.9 includes an alternate, new, normative refclk jitter compliance methodology based on phase noise that provides the same value as the PCI-SIG ® traditional oscilloscope-based methodology (without jitter added from the test environment). To avoid this in PCI Express Base Specification Revision 5.0, Version 0.9 eliminates the refclk compliance load board, which sharpens the clock edges and reduces the oscilloscope's conversion of vertical noise to jitter. In response, the clock and timing industry independently created three different algorithms to subtract jitter added by the test environment. But the steady increase in data rates has reduced timing margins to the point that many low-jitter refclks evaluated to PCI Express Base Specification Revision 4.0 are dominated by jitter introduced by the test environment. Since its inception in 2003, PCI Express has defined reference-clock jitter compliance tests using a real-time oscilloscope. PCI Express ® is one of the few standards defining jitter limits for SERDES reference clocks. Related ResourcesĢ24 Gb/s Per Lane: Options and Challenges This article presents a phase-noise based methodology that provides similar values as TIE jitter derived from an oscilloscope. Since an oscilloscope and phase noise analyzer observe jitter differently, obtaining the same value from both instruments can be challenging. On the other hand, clock-jitter analysis traditionally derives jitter from a phase-noise analyzer due to its inherently lower instrument noise floor. This analysis is straightforward because an oscilloscope-based time-interval error (TIE) jitter measurement observes jitter similar to an actual system (whose jitter filtering may be emulated in software executed in the oscilloscope). Traditionally, real-time oscilloscopes have been used to determine jitter compliance in serial-data signals. This scheme gives designers great freedom to choose reference clocks and budget jitter accordingly. Thus, these standards limit refclk jitter indirectly. Instead, jitter is specified for the serial-data signal, a portion of which originates from the refclk. Most high-speed digital communications standards do not include specifications for reference-clock (refclk) jitter.
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